Power signals for a liquid crystal display (LCD) panel often include VCC, VSS, VGH (positive gate voltage) and VGL (negative gate voltage). Levels of VCC, VSS, VGH and VGL are set to about 3V, 0V, 20V and −10V, respectively. In order to achieve stable operation of a gate driver IC, power must be applied according to a preset power sequence from the outside. A POR (Power On Reset) circuit is accommodated in the gate driver IC in case the power is not applied according to the preset power sequence due to a specific condition of the LCD panel.
In addition, if a chip (integrated circuit (IC)) output is randomly output due to a random output of a logic in the gate driver IC, excessive current may be applied to an output terminal, thereby causing malfunction of the gate driver IC. In order to prevent such a malfunction, the POR (power on reset) circuit is provided in the gate driver IC.
FIGS. 1 and 2 show POR circuits according to the related art.
Referring to FIG. 1, if the VDD linearly increases according to time, the voltage at Node 1 also linearly increases. When the voltage of Node 1 reaches a threshold voltage of an inverter, a RESETB signal changes from a high state to a low state. However, if noise occurs in the VDD or the rising of VDD is short, the RESETB signal is not properly output, and a Flip Flop (F/F) of an internal circuit does not initialize.
The POR circuit shown in FIG. 2 operates similarly to the POR circuit shown in FIG. 1. FIG. 2 is a view representing a circuit, which is improved over the circuit of FIG. 1 by adding a capacitor such that the RESETB signal is properly output even if the rising of the VDD is short. However, static current may be applied to the circuit. In addition, the RESETB signal may be output before the VGH and VGL are stabilized in the gate driver IC, thereby causing malfunction of the gate driver IC.
FIG. 3 is a view representing a power sequence of power applied to the gate driver IC. As shown FIG. 3, in order to achieve stable operation of the gate driver IC, the RESETB output must be stabilized for a predetermined time after the POR operation. That is, as shown in FIG. 3, time point T1 represents an output point of the RESETB signal of the circuit shown in FIG. 2, and T2 is a desired output point of the RESET. That is, in order to allow the gate driver IC to stably operate, the output T2 of the RESET must be stabilized for a predetermined time (T2−T1) after the operation of the POR starts at the time point T1.